G-PathGen: An Efficient GPU-Parallel k-Critical Path Generation Algorithm

Jun 2, 2026·
Che Chang
Yi-Hua Chung
Yi-Hua Chung
,
Cheng-Hsiang Chiu
,
Wan-Luan Lee
,
Boyang Zhang
,
Ulf Schlichtmann
,
Ing-Chao Lin
,
Xiangyao Yu
,
Tsung-Wei Huang
· 0 min read
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Abstract
Critical path generation (CPG) plays a key role in many circuit timing analysis (CTA) applications. As the design complexity continues to increase, CPG runtime has become a major bottleneck in many timing-driven applications. To mitigate this runtime challenge, several CPU-based algorithms have been introduced by both the CTA and parallel computing communities, but they remain slow for large CPG problems. While GPU-accelerated solutions exist, they are often inexact and incur significant overhead from iterative CPU–GPU data transfers, limiting their practical use in CTA applications. To overcome this challenge, we propose G-PathGen, an exact GPU-parallel CPG algorithm targeting CTA applications. G-PathGen introduces efficient kernel algorithms for generating critical paths in parallel and dynamically adjusts the generated path count to maximize GPU utilization while minimizing redundant work. Compared to a state-of-the-art GPU solution, G-PathGen is 1.6x–243.8xfaster when generating one million critical paths on industrial circuit graphs.
Type
Publication
ACM International Conference on Supercomputing (ICS), Belfast, Northern Ireland, UK, 2026
publications
Yi-Hua Chung
Authors
Yi-Hua Chung (she/her)
Ph.D. Student

I am a fourth-year Ph.D. student in the Department of Electrical and Computer Engineering at UW-Madison, advised by Prof. Tsung-Wei (TW) Huang. My research focuses on GPU-accelerated algorithms for compiler optimization, graph partitioning, and design automation applications.

I developed SimPart, a GPU-parallel graph partitioner for logic simulation by integrating disjoint-set and replication-aided strategies, further optimized with conditional CUDA Graphs. I also collaborate with Synopsys to develop GPU-parallel algorithms for gate sizing in an industrial-use EDA tool.