iG-kway: Incremental k-way Graph Partitioning on GPU
Jun 1, 2025·,,,,
,,,·
0 min read
Wan-Luan Lee
Shui Jiang
Dian-Lun Lin
Che Chang
Boyang Zhang
Yi-Hua Chung
Ulf Schlichtmann
Tsung-Yi Ho
Tsung-Wei Huang
Abstract
Recent advances in GPU-accelerated graph partitioning have achieved significant performance gains but remain limited to full graph partitioning, lacking support for incremental updates. This limitation is critical in CAD applications, where circuit graphs undergo iterative, incremental modifications during optimization. We present iG-kway, the first GPU-based incremental k-way graph partitioner. iG-kway features an incrementality-aware data structure and a refinement kernel that efficiently updates only affected vertices with minimal quality loss. Experiments show that iG-kway delivers up to 84x speedup over the state-of-the-art G-kway with comparable partitioning quality.
Type
Publication
ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, 2025

Authors
Yi-Hua Chung
(she/her)
Ph.D. Student
I am a fourth-year Ph.D. student in the Department of Electrical and Computer Engineering at UW-Madison, advised by Prof. Tsung-Wei (TW) Huang. My research focuses on GPU-accelerated algorithms for compiler optimization, graph partitioning, and design automation applications.
I developed SimPart, a GPU-parallel graph partitioner for logic simulation by integrating disjoint-set and replication-aided strategies, further optimized with conditional CUDA Graphs. I also collaborate with Synopsys to develop GPU-parallel algorithms for gate sizing in an industrial-use EDA tool.