iTAP: An Incremental Task Graph Partitioner for Task-parallel Static Timing Analysis
Jan 1, 2025·,,,,,
,,,,·
0 min read
Boyang Zhang
Che Chang
Cheng-Hsiang Chiu
Dian-Lun Lin
Yang Sui
Chih-Chun Chang
Yi-Hua Chung
Wan-Luan Lee
Zizheng Guo
Yibo Lin
Tsung-Wei Huang
Abstract
Recent static timing analysis (STA) tools have utilized task dependency graph (TDG) parallelism to enhance the STA runtime performance. Although TDG parallelism shows promising speedup, the overhead of scheduling a TDG can become dominant as the TDG becomes larger. To minimize the scheduling overhead, several TDG partitioning algorithms have been proposed to reduce the TDG size without affecting its task parallelism. Despite improved performance, existing TDG partitioners all fall short of incremental partitioning, limiting their practical use in STA tools that support timing-driven operations. To overcome this limitation, we propose iTAP, an incremental TDG partitioner to fully leverage the power of TDG partitioning in task-parallel STA applications. Compared to a state-of-the-art full TDG partitioner, iTAP enhances the overall STA performance by up to 2.97x.
Type
Publication
IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, 2025

Authors
Yi-Hua Chung
(she/her)
Ph.D. Student
I am a fourth-year Ph.D. student in the Department of Electrical and Computer Engineering at UW-Madison, advised by Prof. Tsung-Wei (TW) Huang. My research focuses on GPU-accelerated algorithms for compiler optimization, graph partitioning, and design automation applications.
I developed SimPart, a GPU-parallel graph partitioner for logic simulation by integrating disjoint-set and replication-aided strategies, further optimized with conditional CUDA Graphs. I also collaborate with Synopsys to develop GPU-parallel algorithms for gate sizing in an industrial-use EDA tool.