PathGen: An Efficient Parallel Critical Path Generation Algorithm
Jan 2, 2025·,,,
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0 min read
Che Chang
Boyang Zhang
Cheng-Hsiang Chiu
Dian-Lun Lin
Yi-Hua Chung
Wan-Luan Lee
Zizheng Guo
Yibo Lin
Tsung-Wei Huang
Abstract
Critical Path Generation (CPG) is fundamental for many static timing analysis (STA) applications. As the circuit complexity continues to increase, CPG runtime has quickly become the bottleneck due to its time-consuming and iterative nature. Despite many CPG algorithms introduced by existing timers, nearly all of them are limited to a single CPU thread, leading to long runtime for large CPG queries. To mitigate this runtime challenge, we need a parallel CPG algorithm. However, designing a parallel CPG algorithm is very challenging because we need to strategically partition the path search space into multiple groups that can run in parallel while accommodating different slack priorities. To overcome this challenge, we propose PathGen, an efficient CPU-parallel CPG algorithm. PathGen introduces a multi-level queue scheduling framework that can efficiently parallelize the search process of critical paths. Compared to a state-of-the-art single-threaded timer, PathGen is up to 7.4x faster with 16 threads and achieves nearly 100% accuracy when generating one million critical paths on large designs.
Type
Publication
IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, 2025

Authors
Yi-Hua Chung
(she/her)
Ph.D. Student
I am a fourth-year Ph.D. student in the Department of Electrical and Computer Engineering at UW-Madison, advised by Prof. Tsung-Wei (TW) Huang. My research focuses on GPU-accelerated algorithms for compiler optimization, graph partitioning, and design automation applications.
I developed SimPart, a GPU-parallel graph partitioner for logic simulation by integrating disjoint-set and replication-aided strategies, further optimized with conditional CUDA Graphs. I also collaborate with Synopsys to develop GPU-parallel algorithms for gate sizing in an industrial-use EDA tool.