SSTA-X: GPU-Accelerated First-Order Block-Based Statistical Static Timing Analysis
Jan 1, 2026·
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0 min read
Chih-Chun Chang
Yi-Hua Chung
Wan-Luan Lee
Boyang Zhang
Tsung-Wei Huang
Abstract
Statistical static timing analysis (SSTA) is a widely used approach to evaluate circuit timing by modeling gate and path delays as random variables affected by process variations. While Monte Carlo-based SSTA methods offer high accuracy, their reliance on massive sampling leads to very long runtime. To alleviate this runtime overhead, first-order block-based SSTA (FB-SSTA) has been proposed to approximate timing distributions through linear propagation of statistical moments. However, existing FB-SSTA solutions are largely limited to CPU-based parallelism, and their scalability can no longer quickly respond to the ever-growing size of SSTA problems. To overcome this limitation, we propose SSTA-X, a GPU-accelerated FB-SSTA algorithm that significantly enhances the runtime performance by leveraging the massive parallelism of modern GPU. SSTA-X introduces GPU-efficient data structures and kernel algorithms to accelerate key yet time-consuming operations in statistical delay, slew, and moment propagation. Experimental results show that SSTA-X achieves 3.10x–12.47x speedup over a CPU-based baseline on a large-scale design with millions of gates.
Type
Publication
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems (TCAD), to appear

Authors
Yi-Hua Chung
(she/her)
Ph.D. Student
I am a fourth-year Ph.D. student in the Department of Electrical and Computer Engineering at UW-Madison, advised by Prof. Tsung-Wei (TW) Huang. My research focuses on GPU-accelerated algorithms for compiler optimization, graph partitioning, and design automation applications.
I developed SimPart, a GPU-parallel graph partitioner for logic simulation by integrating disjoint-set and replication-aided strategies, further optimized with conditional CUDA Graphs. I also collaborate with Synopsys to develop GPU-parallel algorithms for gate sizing in an industrial-use EDA tool.