XEG: A GPU-Parallel Algorithm for Efficient and Effective E-Graph Extraction

Jan 1, 2027·
Yi-Hua Chung
Yi-Hua Chung
,
Hao-Hsiang Hsiao
,
Cheng-Hsiang Chiu
,
Boyang Zhang
,
Che Chang
,
Joshua San Miguel
,
Tsung-Wei Huang
· 0 min read
Abstract
Equality saturation is a promising compiler optimization approach that addresses the phase-ordering problem by compactly representing equivalent programs in an e-graph. However, extracting the optimal program from a saturated e-graph, known as e-graph extraction, is very time-consuming as the e-graph becomes dense and large. In this paper, we present XEG, a GPU-parallel e-graph extractor that achieves both fast runtime and high solution quality. Specifically, XEG introduces efficient algorithms to establish the e-graph and solution space on GPU and leverages ILP to extract a high-quality solution. Experimental results show that XEG (GPU-based) achieves a 243× average speedup over SmoothE (GPU-based) while improving solution quality by 7%. Compared with e-boost (CPU-based), XEG achieves a 7.73× average speedup while maintaining comparable solution quality. In addition, XEG can operate without ILP as a standalone extractor, achieving a 123× average speedup over egg (CPU-based) with comparable solution quality.
Type
Publication
ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Heraklion, Crete, Greece, 2027
publications
Yi-Hua Chung
Authors
Yi-Hua Chung (she/her)
Ph.D. Student

I am a fourth-year Ph.D. student in the Department of Electrical and Computer Engineering at UW-Madison, advised by Prof. Tsung-Wei (TW) Huang. I am currently a student researcher at Ricursive Intelligence for Fall 2026. My research focuses on GPU acceleration for compiler optimization and design automation.

I developed XEG, a GPU-parallel e-graph extractor that accelerates e-graph extraction while maintaining high solution quality. Previously, I developed SimPart, a GPU-parallel graph partitioner for logic simulation by integrating disjoint-set and replication-aided strategies, further optimized with conditional CUDA Graphs. I also collaborate with Synopsys to develop GPU-parallel algorithms for gate sizing in an industrial EDA tool.