☕️Yi-Hua Chung
(she/her)
Ph.D. Student
Department of Electrical and Computer Engineering, University of Wisconsin-Madison
Professional Summary
I am a fourth-year Ph.D. student in the Department of Electrical and Computer Engineering at UW-Madison, advised by Prof. Tsung-Wei (TW) Huang. My research focuses on GPU-accelerated algorithms for compiler optimization, graph partitioning, and design automation applications.
I developed SimPart, a GPU-parallel graph partitioner for logic simulation by integrating disjoint-set and replication-aided strategies, further optimized with conditional CUDA Graphs. I also collaborate with Synopsys to develop GPU-parallel algorithms for gate sizing in an industrial-use EDA tool.
Education
Ph.D., Electrical and Computer Engineering
2023/09 ─ Present
University of Wisconsin-Madison
M.S., Graduate Institute of Networking and Multimedia
2021/02 ─ 2022/06
National Taiwan University
B.Eng., Biomechatronics Engineering
2016/09 ─ 2021/01
National Taiwan University
Interests
SimPart: A Simple Yet Effective Replication-aided Partitioning Algorithm for Logic Simulation on GPU
Yi-Hua Chung, Shui Jiang, Wan Luan Lee, Yanqing Zhang, Haoxing Ren, Tsung-Yi Ho, and Tsung-Wei Huang
International European Conference on Parallel and Distributed Computing (Euro-Par), 2025
Professional Experience
Student Researcher
Ricursive Intelligence
Technical Intern, R&D Team, EDA Group
Synopsys, Sunnyvale
Mentored by Nahmsuk Oh | Manager: Malleswara Gupta | Collaborated with Vishal Khandelwal, Aditya Shiledar, and Sudipto Kundu.
- Designed and implemented GPU-parallel kernel algorithms for LibCell selection in gate sizing, achieving a 38.13x speedup over the 16-core CPU-based Synopsys industrial sizer.
- Integrated the GPU kernels into Synopsys Fusion Compiler, enabling heterogeneous CPU-GPU co-processing for gate sizing; published in the Euro-Par PhD Symposium 2025.
Full-Time Research Assistant
Institute of Information Science, Academia Sinica
Advised by Prof. Bo-Yin Yang, Prof. Daniel J. Bernstein, and Prof. Tanja Lange.
- Developed GPU-accelerated big-integer multiplication with NVIDIA-level performance for post-quantum cryptosystems.
- Accelerated NTRU and NTRU Prime lattice-based cryptosystems on Cortex-A72 with vectorized polynomial multipliers, achieving up to 6.7x faster multiplications and 7.67x faster key generation compared to state-of-the-art; published in the Indocrypt, 2023.
Teaching & Service
Teaching Assistant, Advanced Computer Architecture II
Department of ECE, University of Wisconsin-Madison; Instructor: Prof. Joshua San Miguel
- Built a cross-platform Docker environment for gem5 simulation and benchmarking on Linux, macOS, and Windows.
- Recognized with the Department of ECE Gerald Holdridge Teaching Excellence Award (2026)
Teaching Assistant, Computer Architecture
Department of CSIE, National Taiwan University; Instructor: Prof. Shih-Hao Hung
Department of ECE The Gerald Holdridge Teaching Excellence Award, 2026
ACM/IEEE DAC Young Student Fellowship, 2024, 2025
NTUEE-1975 Innovation and Entrepreneurship Fund Award, College of Electrical Engineering and Computer Science, National Taiwan University
2022 Future Tech Awards, National Science and Technology Council, R.O.C.
Best Paper Award, 9th International Multi-Conference on Engineering and Technology Innovation 2020
Outstanding Performance Award, NTU-IBM Q System 2020 Q-Camp, Hackathon, Sep 2020
- Expert: C/C++, CUDA C/C++, OpenMP, ARM Intrinsic, ARM Assembly, Linux, Shell
- Experienced: Python, C#, Qiskit, JavaScript, WebGL