Yi-Hua Chung
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ABOUT ME

Research Interests

  • Parallel and Heterogeneous Computing (CPU and GPU)
  • High-Performance Computing (GPU and ARM Cortex-M)
  • Design Automation

Infomation

I’m a first-year Ph.D. student at the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison, advised by Prof. Tsung-Wei (TW) Huang.
I am currently engaged in fault simulation, focusing on expediting the testing and verification process by implementing GPU-accelerated strategies such as partitioning, pruning, and early break. These techniques aim to enhance efficiency in fault detection. In addition to our ongoing fault simulation project, I have conducted a comprehensive survey of papers within the EDA research field, specifically focusing on acceleration strategies to expedite global routing and gate-sizing problems.

Education

Ph.D., Department of Electrical and Computer Engineering

  • University of Wisconsin-Madison, WI, the USA. 2023/09 - Present
  • GPA: 4.00/4.00 (Fall 23)
  • Courses: High Performance Computing and Computer-Aided Design for VLSI

Master of Science, Graduate Institute of Networking and Multimedia

  • National Taiwan University, Taipei, Taiwan. 2021/02 - 2022/06
  • Master Thesis: Enlarging Quantum Circuit Simulation and Analysis with Non-Volatile Memories
  • GPA: 4.25/4.30, Graduation Rank: 1/47

Bachelor of Engineering, Department of Biomechatronics Engineering

  • National Taiwan University, Taipei, Taiwan. 2016/09 - 2021/01
  • Bachelor Thesis: Development of a Small Intelligent Weather Station for Agricultural Applications
  • GPA: 3.72/4.30

Work Experience

Graduate Research Assistant, Department of Electrical and Computer Engineering, University of Wisconsin-Madison. 2023/08-present

  • Led by Prof. Tsung-Wei (TW) Huang
  • Researched GPU-accelerated testing and verification algorithms, especially on fault simulation
  • Accelerated VLSI routing algorithm utilizing GPU that speeds up the state-of-the-art from 2x to 11x
  • Researched parallel and heterogeneous gate-sizing algorithms in timing-driven optimization

Full-Time Research Assistant, Institute of Information Science, Academia Sinica. 2022/08-2023/03

  • Led by Prof. Bo-Yin Yang, Prof. Daniel J. Bernstein, and Prof. Tanja Lange
  • Accelerated big-integer multiplication by adopting the Fast NTT algorithm with warp primitive technique and inline PTX on GPU
  • Implemented lattice-based cryptosystems, including NTRU and NTRU Prime, on Cortex-A72 and accelerated the program by adopting fast NTT, Toom-Cook algorithm, and Schönhage-Strassen algorithm under the ARMv8-A architecture

Research Assistant, “Emerging Technology Design Automation in the Post-Moore Era” Project, National Taiwan University. 2021/07-2022/08

  • Led by Prof. Shih-Hao Hung, Prof. Jie-Hong Roland Jiang, and Prof. Chung-Yang Huang
  • Researched quantum-related topics, including quantum annealing, quantum simulation, and quantum machine learning
  • Led a study group and assisted labmates on large-scale simulated quantum annealing on multi-GPU

Research Assistant, Mass and Energy Transfer Lab, National Taiwan University. 2020/01-2020/08

  • Led by Prof. Chen Kang Huang
  • Constructed a weather box equipped with rainfall prediction, frosting forecast, and lightning detection functions with a wireless connection and built-in decision mode to deliver an early warning message to users to avoid a decrease in profit

Teaching Assistant, Department of Computer Science and Information Engineering, National Taiwan University. 2021/09-2022/01

  • Course: Computer Architecture; Opened by Prof. Shih-Hao Hung

Publications

Awards

  • ACM/IEEE DAC Young Student Fellowship, 2024
  • NTUEE-1975 Innovation and Entrepreneurship Fund Award, College of Electrical Engineering and Computer Science, National Taiwan University
  • 2022 Future Tech Awards, National Science and Technology Council, R.O.C.
  • Best Paper Award, 9th International Multi-Conference on Engineering and Technology Innovation 2020
  • Outstanding Performance Award, NTU-IBM Q System 2020 Q-Camp, Hackathon, Sep 2020

Projects

  • Variational Neural Annealing - Recurrent Neural Network Wave Functions
    • Reproduced works from Waterloo University to solve the 1D and 2D Ising problems with 1D and 2D RNN models
    • Compared the solution quality and cost time between variational neural annealing and classical simulated quantum annealing
  • 2022 QOSF Cohort-5 (Mentorship program)
    • Constructed quantum circuits of Grover’s algorithm to find the best solution for the quantum tic-tac-toe
  • Quantum 2D DNA Pattern Matching
    • Bo-Cheng Jhu, Yi-Hua Chung, Nai-Wei Syu, Ting Wu, and Bo-Syun Lin
  • Completed competition 4/4, IBM Quantum Challenge 2020, May 2020

Skills

  • Expert: C/C++, CUDA C/C++, OpenMP, ARM Intrinsic, ARM Assembly, Linux, Shell
  • Experienced: Python, C#, Qiskit, JavaScript, WebGL

More About Me

Before joining TW’s lab, I worked as a full-time research assistant at the Institute of Information Science, Academia Sinica, under the supervision of Prof. Bo-Yin Yang, Prof. Daniel J. Bernstein, and Prof. Tanja Lange, studying assembly-optimized implementations in lattice-based post-quantum systems and implementing a library for big integer multiplication on GPU by employing number-theoretic transformations algorithm. I pursued my M.S. degree, instructed by Prof. Shih-Hao Hung. I worked on two notable projects, including enhancing quantum circuit simulation and analysis utilizing non-volatile memories and accelerating simulated quantum annealing by leveraging GPU and tensor cores.

I am passionate about solving Sudoku. I often watch videos on YouTube presenting different problem-solving skills by professional individuals.
I also like essential oils; the scent of various woody essential oils makes me relax.

Don’t let anyone rob you of your imagination, your creativity, or your curiosity. It’s your place in the world; it’s your life. Go on and do all you can with it, and make it the life you want to live. –Mae Jemison