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ABOUT ME

Research Interests

  • Parallel and Heterogeneous Computing (CPU and GPU)
  • High-Performance Computing (GPU and ARM Cortex-M)
  • Design Automation

Information

I am a second-year Ph.D. student in the Department of Electrical and Computer Engineering at UW-Madison, advised by Prof. Tsung-Wei (TW) Huang. My research focuses on high-performance computing, parallel computing, and GPU acceleration for design automation problems.

Currently, I am particularly interested in developing GPU-friendly partitioning algorithms to accelerate logic simulation on GPU and exploring hybrid CPU-GPU computing to optimize the runtime of gate-sizing on GPU.

Education

Ph.D., Department of Electrical and Computer Engineering

  • University of Wisconsin-Madison, WI, the USA. 2023/09 - Present
  • GPA: 4.00/4.00 (Fall 24)

Master of Science, Graduate Institute of Networking and Multimedia

  • National Taiwan University, Taipei, Taiwan. 2021/02 - 2022/06
  • Master Thesis: Enlarging Quantum Circuit Simulation and Analysis with Non-Volatile Memories
  • GPA: 4.25/4.30, Graduation Rank: 1/47

Bachelor of Engineering, Department of Biomechatronics Engineering

  • National Taiwan University, Taipei, Taiwan. 2016/09 - 2021/01
  • Bachelor Thesis: Development of a Small Intelligent Weather Station for Agricultural Applications

Work Experience

Graduate Research Assistant, Department of Electrical and Computer Engineering, University of Wisconsin-Madison. 2023/08-present

  • Led by Prof. Tsung-Wei (TW) Huang
  • Researched GPU-accelerated testing and verification algorithms, especially on fault simulation
  • Accelerated VLSI routing algorithm utilizing GPU that speeds up the state-of-the-art from 2x to 11x
  • Researched parallel and heterogeneous gate-sizing algorithms in timing-driven optimization

Technical Internship, R&D Team, EDA Group, Synopsys - Sunnyvale. 2024/06-2024/12

  • Leveraging hybrid-computing of CPU-GPU co-processing into the Fusion Compiler tool
  • Accelerating Gate-sizing problem by adopting GPUs in Fusion Compiler tool with 4x-8x compared with multi-cores CPU version

Publications

  • Shui Jiang, Yi-Hua Chung, Chih-Chun Chang, Tsung-Yi Ho, and Tsung-Wei Huang, “BQSim: GPU-accelerated Batch Quantum Circuit Simulation using Decision Diagram,ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Rotterdam, Netherlands, 2025
  • Boyang Zhang, Che Chang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yang Sui, Chih-Chun Chang, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, and Tsung-Wei Huang, iTAP: An Incremental Task Graph Partitioner for Task-parallel Static Timing Analysis, IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, 2025
  • Che Chang, Boyang Zhang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, and Tsung-Wei Huang, PathGen: An Efficient Parallel Critical Path Generation Algorithm, IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, 2025

Awards

  • ACM/IEEE DAC Young Student Fellowship, 2024
  • NTUEE-1975 Innovation and Entrepreneurship Fund Award, College of Electrical Engineering and Computer Science, National Taiwan University
  • 2022 Future Tech Awards, National Science and Technology Council, R.O.C.
  • Best Paper Award, 9th International Multi-Conference on Engineering and Technology Innovation 2020
  • Outstanding Performance Award, NTU-IBM Q System 2020 Q-Camp, Hackathon, Sep 2020

Skills

  • Expert: C/C++, CUDA C/C++, OpenMP, ARM Intrinsic, ARM Assembly, Linux, Shell
  • Experienced: Python, C#, Qiskit, JavaScript, WebGL

Last Updated on Feb 7, 2025