Research Interests
- Parallel and Heterogeneous Computing (CPU and GPU)
- High-Performance Computing (GPU and ARM Cortex-M)
- Design Automation
Infomation
I’m a Ph.D. student at the Department of ECE at UW-Madison, advised by Prof. Tsung-Wei (TW) Huang. I am currently engaged in:
- Gate-sizing project: Exploiting hybrid-computing of CPU-GPU co-processing into the Fusion Compiler tool to accelerate the runtime performance. Synopsys, R&D Team, EDA Group.
- Fault simulation project: Concentrating on expediting the testing and verification process by adopting GPUs and designing partitioning algorithms. NVIDIA, Design Automation Research Team.
Education
Ph.D., Department of Electrical and Computer Engineering
- University of Wisconsin-Madison, WI, the USA. 2023/09 - Present
- GPA: 4.00/4.00 (Fall 24)
Master of Science, Graduate Institute of Networking and Multimedia
- National Taiwan University, Taipei, Taiwan. 2021/02 - 2022/06
- Master Thesis: Enlarging Quantum Circuit Simulation and Analysis with Non-Volatile Memories
- GPA: 4.25/4.30, Graduation Rank: 1/47
Bachelor of Engineering, Department of Biomechatronics Engineering
- National Taiwan University, Taipei, Taiwan. 2016/09 - 2021/01
- Bachelor Thesis: Development of a Small Intelligent Weather Station for Agricultural Applications
- GPA: 3.72/4.30
Work Experience
Technical Internship, R&D Team, EDA Group, Synopsys - Sunnyvale. 2024/06-2024/12
- Leveraging hybrid-computing of CPU-GPU co-processing into the Fusion Compiler tool
- Accelerating Gate-sizing problem by adopting GPUs in Fusion Compiler tool with 4x-8x compared with multi-cores CPU version
Graduate Research Assistant, Department of Electrical and Computer Engineering, University of Wisconsin-Madison. 2023/08-present
- Led by Prof. Tsung-Wei (TW) Huang
- Researched GPU-accelerated testing and verification algorithms, especially on fault simulation
- Accelerated VLSI routing algorithm utilizing GPU that speeds up the state-of-the-art from 2x to 11x
- Researched parallel and heterogeneous gate-sizing algorithms in timing-driven optimization
Full-Time Research Assistant, Institute of Information Science, Academia Sinica. 2022/08-2023/03
- Led by Prof. Bo-Yin Yang, Prof. Daniel J. Bernstein, and Prof. Tanja Lange
- Accelerated big-integer multiplication by adopting the Fast NTT algorithm with warp primitive technique and inline PTX on GPU
- Implemented lattice-based cryptosystems, including NTRU and NTRU Prime, on Cortex-A72 and accelerated the program by adopting fast NTT, Toom-Cook algorithm, and Schönhage-Strassen algorithm under the ARMv8-A architecture
Research Assistant, “Emerging Technology Design Automation in the Post-Moore Era” Project, National Taiwan University. 2021/07-2022/08
- Led by Prof. Shih-Hao Hung, Prof. Jie-Hong Roland Jiang, and Prof. Chung-Yang Huang
- Researched quantum-related topics, including quantum annealing, quantum simulation, and quantum machine learning
- Led a study group and assisted labmates on large-scale simulated quantum annealing on multi-GPU
Research Assistant, Mass and Energy Transfer Lab, National Taiwan University. 2020/01-2020/08
- Led by Prof. Chen Kang Huang
- Constructed a weather box equipped with rainfall prediction, frosting forecast, and lightning detection functions with a wireless connection and built-in decision mode to deliver an early warning message to users to avoid a decrease in profit
Teaching Assistant, Department of Computer Science and Information Engineering, National Taiwan University. 2021/09-2022/01
- Course: Computer Architecture; Opened by Prof. Shih-Hao Hung
Publications
- Boyang Zhang, Che Chang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yang Sui, Chih-Chun Chang, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, and Tsung-Wei Huang, “iTAP: An Incremental Task Graph Partitioner for Task-parallel Static Timing Analysis,” IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, 2025
- Che Chang, Boyang Zhang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, and Tsung-Wei Huang, “PathGen: An Efficient Parallel Critical Path Generation Algorithm,” IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, 2025
- Chen, Han-Ting, Yi-Hua Chung, Vincent Hwang, and Bo-Yin Yang. “Algorithmic Views of Vectorized Polynomial Multipliers–NTRU (2023).“ Indocrypt, 2023.
- Chen, Han-Ting, Yi-Hua Chung, Vincent Hwang, Chi-Ting Liu, and Bo-Yin Yang. “Algorithmic Views of Vectorized Polynomial Multipliers for NTRU and NTRU Prime (Long Paper).“ Cryptology ePrint Archive, Paper 2023/541. 2023.
- Implementations: Github
- Yi-Hua Chung. 2022. Enlarging quantum circuit simulation and analysis with non-volatile memories. Master’s thesis. National Taiwan University, No. 1, Sec. 4, Roosevelt Rd., Taipei 106216, Taiwan (R.O.C.).
- Chung, Yi-Hua, Cheng-Jhih Shih, and Shih-Hao Hung. “Accelerating simulated quantum annealing with GPU and tensor cores.“ In International Conference on High Performance Computing, pp. 174-191. Cham: Springer International Publishing, 2022.
- Chung, Yi-Hua, Huang Jun-Fu, Hu Yuan-Chen, and Huang Chen-Kang. “Development of a Small Intelligent Weather Station for Agricultural Applications.“ Advances in Technology Innovation 6, no. 2 (2021): 74.
- [Best Paper Award] in the 9th international multi-conference on Engineering and Technology Innovation, 2020.
![[Best Paper Award]](/uploads/Best Award.png){kind=link}
Awards
- ACM/IEEE DAC Young Student Fellowship, 2024
- NTUEE-1975 Innovation and Entrepreneurship Fund Award, College of Electrical Engineering and Computer Science, National Taiwan University
- 2022 Future Tech Awards, National Science and Technology Council, R.O.C.
- Best Paper Award, 9th International Multi-Conference on Engineering and Technology Innovation 2020
- Outstanding Performance Award, NTU-IBM Q System 2020 Q-Camp, Hackathon, Sep 2020
Skills
- Expert: C/C++, CUDA C/C++, OpenMP, ARM Intrinsic, ARM Assembly, Linux, Shell
- Experienced: Python, C#, Qiskit, JavaScript, WebGL
Projects
- Variational Neural Annealing - Recurrent Neural Network Wave Functions
- Reproduced works from Waterloo University to solve the 1D and 2D Ising problems with 1D and 2D RNN models
- Compared the solution quality and cost time between variational neural annealing and classical simulated quantum annealing
- 2022 QOSF Cohort-5 (Mentorship program)
- Constructed quantum circuits of Grover’s algorithm to find the best solution for the quantum tic-tac-toe
- Quantum 2D DNA Pattern Matching
- Bo-Cheng Jhu, Yi-Hua Chung, Nai-Wei Syu, Ting Wu, and Bo-Syun Lin
- Completed competition 4/4, IBM Quantum Challenge 2020, May 2020
More About Me
Before joining TW’s lab, I worked as a full-time research assistant at the Institute of Information Science, Academia Sinica, under the supervision of Prof. Bo-Yin Yang, Prof. Daniel J. Bernstein, and Prof. Tanja Lange, studying assembly-optimized implementations in lattice-based post-quantum systems and implementing a library for big integer multiplication on GPU by employing number-theoretic transformations algorithm. I pursued my M.S. degree, instructed by Prof. Shih-Hao Hung. I worked on two notable projects, including enhancing quantum circuit simulation and analysis utilizing non-volatile memories and accelerating simulated quantum annealing by leveraging GPU and tensor cores.
I am passionate about solving Sudoku. I often watch videos on YouTube presenting different problem-solving skills by professional individuals.
Don’t let anyone rob you of your imagination, your creativity, or your curiosity. It’s your place in the world; it’s your life. Go on and do all you can with it, and make it the life you want to live. –Mae Jemison
Last Updated on Oct 1, 2024