Research Interests
- High-Performance Computing
- GPU Parallel Computing
- Design Automation
Information
I am a third-year Ph.D. student in the Department of Electrical and Computer Engineering at UW-Madison, advised by Prof. Tsung-Wei (TW) Huang. My research focuses on GPU-accelerated algorithms for compiler optimization, graph partitioning, and design automation applications.
I developed SimPart, a GPU-parallel graph partitioner for logic simulation by integrating disjoint-set and replication-aided strategies, further optimized with conditional CUDA Graphs. I also collaborate with Synopsys to develop GPU-parallel algorithms for gate sizing in an industrial-use EDA tool.
Education
Ph.D., Department of Electrical and Computer Engineering
- University of Wisconsin-Madison, WI, the USA. 2023/09 - Present
- GPA: 4.00/4.00 (Spring 25)
Master of Science, Graduate Institute of Networking and Multimedia
- National Taiwan University, Taipei, Taiwan. 2021/02 - 2022/06
- Master Thesis: Enlarging Quantum Circuit Simulation and Analysis with Non-Volatile Memories
- GPA: 4.25/4.30, Graduation Rank: 1/47
Bachelor of Engineering, Department of Biomechatronics Engineering
- National Taiwan University, Taipei, Taiwan. 2016/09 - 2021/01
- Bachelor Thesis: Development of a Small Intelligent Weather Station for Agricultural Applications
Work Experience
Graduate Research Assistant, Department of Electrical and Computer Engineering, University of Wisconsin-Madison. 2023/08-present
- Led by Prof. Tsung-Wei (TW) Huang
- Developed SimPart, a simple yet effective GPU-accelerated graph partitioner, achieving 23× faster partitioning and 1.58× faster GPU logic simulation runtime over the state-of-the-art partitioner.
- Developed a C++ equality saturation framework for compiler optimization to enable large-scale program transformations.
Technical Internship, R&D Team, EDA Group, Synopsys - Sunnyvale. 2024/06-2024/12
- Developed GPU-parallel kernel algorithms, achieving 38.13× speedup over a 16-core CPU industrial sizer.
- Integrated GPU kernels into a Synopsys EDA tool to enable heterogeneous CPU–GPU co-processing for gate sizing.
- Research results accepted for publication: "Accelerating Gate Sizing using GPU," Euro-Par PhD Symposium 2025.
Publications
- Yi-Hua Chung, Shui Jiang, Wan Luan Lee, Yanqing Zhang, Haoxing Ren, Tsung-Yi Ho, and Tsung-Wei Huang, “SimPart: A Simple Yet Effective Replication-aided Partitioning Algorithm for Logic Simulation on GPU,“ International European Conference on Parallel and Distributed Computing (Euro-Par), Dresden, Germany, 2025
- Yi-Hua Chung, Nahmsuk Oh, Malleswara Gupta Balabhadra Naga Venkata, Aditya Shiledar, Sudipto Kundu, Vishal Khandelwal, and Tsung-Wei Huang, “Accelerating Gate Sizing using GPU,” International European Conference on Parallel and Distributed Computing (Euro-Par) PhD Symposium, Dresden, Germany, 2025
- Wan-Luan Lee, Shui Jiang, Dian-Lun Lin, Che Chang, Boyang Zhang, Yi-Hua Chung, Ulf Schlichtmann, Tsung-Yi Ho, and Tsung-Wei Huang, “iG-kway: Incremental k-way Graph Partitioning on GPU,“ ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, 2025
Awards
- ACM/IEEE DAC Young Student Fellowship, 2025
- ACM/IEEE DAC Young Student Fellowship, 2024
- NTUEE-1975 Innovation and Entrepreneurship Fund Award, College of Electrical Engineering and Computer Science, National Taiwan University
- 2022 Future Tech Awards, National Science and Technology Council, R.O.C.
- Best Paper Award, 9th International Multi-Conference on Engineering and Technology Innovation 2020
- Outstanding Performance Award, NTU-IBM Q System 2020 Q-Camp, Hackathon, Sep 2020
Skills
- Expert: C/C++, CUDA C/C++, OpenMP, ARM Intrinsic, ARM Assembly, Linux, Shell
- Experienced: Python, C#, Qiskit, JavaScript, WebGL
Hobbies
- Tennis, Table tennis, Volleyball Sudoku Piano